Fin metal-oxide-semiconductor field effect transistor (FinMOSFET, or finFET) provides solutions to metal-oxide-semiconductor field effect transistor (MOSFET) scaling problems at, and below, the 45 nm node of semiconductor technology. A finFET comprises at least one narrow (preferably<30 nm wide) semiconductor fin gated on at least two opposing sides of each of the at least one semiconductor fin. Prior art finFET structures are typically formed on a semiconductor-on-insulator (SOI) substrate, because of low source/drain diffusion to substrate capacitance and ease of electrical isolation by shallow trench isolation structures.
A feature of a finFET is a gate electrode located on at least two sides of the channel of the transistor. Due to the advantageous feature of full depletion in a finFET, the increased number of sides on which the gate electrode controls the channel of the finFET enhances the controllability of the channel in a finFET compared to a planar MOSFET. The improved control of the channel allows smaller device dimensions with less short channel effects as well as larger electrical current that can be switched at high speeds. A finFET device has faster switching times, equivalent or higher current density, and much improved short channel control than the mainstream CMOS technology utilizing similar critical dimensions.
In a typical finFET structure, at least one horizontal channel on a vertical sidewall is provided within the semiconductor “fin” that is set sideways, or edgewise, upon a substrate. Typically, the fin comprises a single crystalline semiconductor material with a substantially rectangular cross-sectional area. Also typically, the height of the fin is greater than width of the fin to enable higher on-current per unit area of semiconductor area used for the finFET structure. In order to obtain desirable control of short channel effects (SCEs), the semiconductor fin is thin enough in a device channel region to ensure forming fully depleted semiconductor devices. Typically, the thickness, or the horizontal width, of a fin in a finFET is less than two-thirds of its gate length in order to obtain good control of the short channel effect.
While providing improved MOSFET performance, the finFETs, however, pose unique design challenges. While planar MOSFET devices have virtually no limit on the width of the device above the lithographical minimum dimension and therefore, the size of planar MOSFETs may be adjusted arbitrarily, typical finFETs have identical vertical dimensions for the fins, thereby limiting the size of the finFET to integer multiples of a minimum size finFET for a given channel length. In other words, for the control of the on-current and the off-current of transistors, planar MOSFETs provide two parameters, which are the width, W and the length, L of the channel but finFETs provide only one parameter, which is the length, L of the finFET since the height of the fin, and consequently the width of the channel is fixed for all finFETs. Therefore, for a given transistor length, L, which defines the ratio of the on-current to off-current, the amount of on-current from an individual fin is fixed. Using multiple fins for a finFET provide integer multiples for the total current but non-integer fractions or non-integer multiples of the on-current of an individual fin requires non-obvious or elaborate processing schemes and/or structures. Further, transistors with different on-currents are often required in the design of high performance integrated circuits.
Further, prior art finFETs typically suffer from deviations of surfaces of the fins from an intended crystallographic orientation which may be caused by a taper in the sidewalls of the fins during an anisotropic etch. Such deviations in the crystallographic orientation of the surfaces of the fins cause increase in leakage current, thereby degrading device performance.
In addition, prior art finFETs allow formation of field effect transistors on surfaces of a single crystalline substrate, which result in limited choice of crystallographic orientations.
In view of the above, there exists a need to provide a field effect transistor providing the benefits of a finFET, while allowing continuous variation of on-current.
Further, there exists a need to provide a field effect transistor in which surface orientations of surfaces of fins are aligned to crystallographic orientations so that leakage current of the field effect transistor may be reduced.
Yet further, there exists a need to provide semiconductor structure offering expanded choices for crystallographic orientations for channels of field effect transistors.